How a CPU Executes Code

A modern CPU executes billions of instructions every second. To appreciate how extraordinary that is, consider that each instruction might be as simple as “add these two numbers” or “copy this value from one memory location to another.” The sophistication of modern software emerges entirely from the rapid, reliable execution of enormous numbers of these tiny operations. Understanding how that actually happens — at the hardware level — makes the whole idea of programming far more concrete.

What Is an Instruction?

A CPU does not understand Python, JavaScript, or C. Those languages are high-level abstractions that must be translated, through compilation or interpretation, into machine code: sequences of binary numbers that encode specific operations the processor’s circuitry is designed to carry out.

Each operation the CPU can perform is part of its instruction set architecture (ISA). The ISA is the contract between the hardware and the software: it defines exactly which operations the processor can execute and how those operations are encoded in binary. Intel and AMD processors use the x86-64 ISA; Apple’s M-series chips and most smartphones use ARM. Programs compiled for one ISA cannot run on the other without modification or emulation.

Common instruction types include arithmetic (add, subtract, multiply), logic (AND, OR, NOT), data movement (load a value from memory into a register, store a value from a register back to memory), and control flow (jump to a different part of the program, call a function, return from a function).

Registers: The CPU’s Scratchpad

Before a CPU can do arithmetic, it needs somewhere to hold the numbers it is working with. Main memory (RAM) is too slow to keep up with a processor running at billions of cycles per second. Instead, CPUs contain a small number of extremely fast storage locations called registers — typically 16 to 32 in a modern general-purpose CPU, each holding a fixed number of bits (usually 64).

Registers are the CPU’s scratchpad. An instruction might say: “Take the value in register R1, add the value in register R2, and put the result in register R3.” The entire operation happens inside the chip, with no access to RAM required.

When data needs to come from RAM (or when results need to be written back), explicit load and store instructions move data between registers and memory. This is one reason that memory-heavy programs can be slower than CPU-bound ones: every round trip to RAM costs time.

The Fetch-Decode-Execute Cycle

The CPU repeats the same three-step process billions of times per second:

Fetch. The processor reads the next instruction from memory. It knows where to look because it maintains a special register called the program counter (PC), which holds the memory address of the next instruction to execute. After each fetch, the program counter is automatically incremented to point at the next instruction.

Decode. The raw binary instruction is passed to the decoder, a circuit that figures out what operation the instruction represents. “Binary pattern 0x01 with these operands means: add these two registers.” The decoder translates the instruction into a set of signals that activate the right parts of the chip.

Execute. The decoded instruction is sent to the appropriate functional unit. Arithmetic and logic operations go to the ALU (Arithmetic Logic Unit). Memory operations go to the load/store unit. The result is written to a register or back to memory, and the cycle begins again with the next instruction.

The Control Unit and the ALU

The control unit is the part of the CPU that orchestrates everything. It fetches instructions, manages the program counter, sends decoded signals to the right functional units, and handles the logistics of getting data where it needs to be. Think of it as the conductor of an orchestra: it does not play an instrument itself, but it keeps every section in time.

The ALU is the part that does actual computation — addition, subtraction, bitwise operations (AND, OR, XOR, NOT, shifts). Modern CPUs contain several ALUs operating in parallel, as well as separate FPUs (Floating-Point Units) for decimal arithmetic, which requires different circuitry.

Clock Speed and the Clock Cycle

Every operation inside a CPU is synchronised to a clock — an oscillating crystal that switches between high and low voltage billions of times per second. Each full oscillation is one clock cycle, and the number of cycles per second is the clock speed, measured in gigahertz (GHz). A 4 GHz processor completes four billion cycles per second.

Not every instruction completes in a single clock cycle. Simple arithmetic might take one cycle; a memory access from RAM might take hundreds if the data is not already in the cache. Clock speed alone is therefore a poor indicator of real-world performance — what matters is how many useful instructions are completed per second across all cores.

Pipelining: Parallel Progress

The fetch-decode-execute cycle makes it sound like the CPU sits idle during decoding and execution. Modern processors avoid this waste using pipelining: while one instruction is being executed, the next is being decoded, and the one after that is being fetched — simultaneously, like an assembly line.

A five-stage pipeline can have five instructions “in flight” at the same time, each at a different stage of the process. The pipeline does not make any single instruction faster, but it dramatically increases the number of instructions completed per unit of time. Modern CPUs have pipelines with 10 to 20 stages or more.

Pipelining introduces a complication: hazards. If instruction B depends on the result of instruction A, which has not finished executing yet, the pipeline must stall. Branch instructions — which change the program counter based on a condition — are particularly problematic, because the processor does not know which instruction to fetch next until the branch condition has been evaluated. CPUs use branch prediction logic to guess which path will be taken and speculatively fetch and decode instructions along that path. Most of the time the guess is correct; when it is wrong, the pipeline must be flushed and the work discarded.

Caches: Bridging the Speed Gap

RAM is orders of magnitude slower than the CPU. If the processor had to fetch every value directly from RAM, the pipeline would spend most of its time stalled waiting for data. The solution is a hierarchy of caches: small, extremely fast memory banks built directly onto the chip.

L1 cache is the fastest and smallest, typically 32–64 KB per core, sitting just a few nanometres from the execution units. L2 cache is larger but slightly slower. L3 cache is shared across cores and can be tens of megabytes. If the data needed is in L1, the processor retrieves it in one or two cycles; from L3, it might take 40. From main RAM: hundreds of cycles.

Multiple Cores

A single-core processor can only execute one stream of instructions at a time. Modern CPUs contain multiple cores — each a self-contained fetch-decode-execute engine with its own registers, L1, and L2 cache. A six-core CPU can execute six independent instruction streams in parallel.

This is why long-running tasks that can be divided into independent subtasks — video encoding, physics simulation, database queries — benefit enormously from more cores. Tasks that are inherently sequential, like following a chain of logic where each step depends on the previous one, are less able to exploit additional cores.

From Code to Silicon

The path from the code you write to instructions running on silicon involves several layers of translation — compiler, assembler, operating system scheduler, CPU microcode — each adding abstraction and convenience. But at the bottom of every layer is the same ancient cycle, running faster than the eye can track: fetch an instruction, decode what it means, execute it, and fetch the next. Billions of times per second, in every device you own.